Journal Papers
  1. Wireless Data Transfer System
    F. Plessas, Bochtis, A. Miaoudakis, G. Kalivas, K. Efstathiou.
    Tehnika(2002), vol. 178, January 2002, pp. 82 - 87. 
  2. Design-Space Exploration of the most widely used Cryptography Algorithms
    I. Papaefstathiou, V. Papaefstathiou and C. Sotiriou.
    Elsevier Journal on Microprocessors and Microsystems, special issue on Secure Computing Platforms, 4 pages, 2003. 
  3. Design and Implementation of a DCS 1800 Receiver
    F. Plessas, P. Simitsakis, G. Kalivas.
    Tehnika a Elektrotehnika, vol. 53, no. 6, 2004 pp. 1-8. 
  4. A Theoretical and Experimental Study of the Phase Noise Behaviour of a Dual-Loop Frequency Synthesizer for 5-GHz WLANs
    F. Plessas, S. Vatti, G. Kalivas.
    Journal of Circuits, Systems and Computers, vol. 16, no. 4, Aug 2007, pp. 577-588. 
  5. A 5-GHz Injection-Locked Phase Locked Loop
    F. Plessas, G. Kalivas.
    Microwave and Optical Technology Letters, vol. 46, no. 1, July 2005, pp. 80-84. 
  6. De-synchronization: synthesis of asynchronous circuits from synchronous specifications
    J. Cortadella, A. Kondratyev, L. Lavagno and C. Sotiriou.
    IEEE Transactions on Computer-Aided Design (IEEE-TCAD), Volume 25, Issue 10, pp. 1904-1921, 15 pages, October 2006. 
  7. High Rate Data Synchronization in GALS SoCs
    R. Dobkin, R. Ginosar and C. Sotiriou.
    IEEE Transactions on Very Large Scale Integration (VLSI) Systems, (IEEE-VLSI), Volume 14, Issue 10, pp. 1063-1074, 16 pages, 2006. 
  8. A Subharmonically Injected Phase Locked Loop for 5-GHz Applications
    F. Plessas and G. Kalivas.
    Microwave and Optical Technology Letters, vol. 48, no. 11, Nov. 2006, pp. 2158-2162.  
  9. Subharmonic injection locking and self-oscillating mixing
    F. Plessas, A. Papalambrou, G. Kalivas.
    International Journal of Circuit Theory and Applications, vol. 37, Issue 3, Apr. 2009, pp. 479-502.  
  10. A 0.5 - 5.5 GHz Distributed Low Noise Amplifier
    E. Lourandakis, F. Plessas, G. Kalivas.
    ECTI Transactions on Electrical Engineering, Electronics and Communications, vol. 6, Feb. 2008, pp. 26-31. 
  11. A 5-GHz Subharmonic Injection-Locked Oscillator and Self-Oscillating Mixer
    F. Plessas, A. Papalambrou, G. Kalivas.
    IEEE Transactions on Circuits and Systems II, vol. 55, no. 7, July 2008, pp. 633-637. 
  12. Ultra wideband, low-power, 3-5.6 GHz CMOS voltage-controlled oscillator
    A. Tsitouras, F. Plessas.
    Microelectronics Journal, vol. 40, Issue 6, June 2009, pp. 897-904.  
  13. Ultra-Wideband, Low-Power, Inductorless, 3.1-4.8 GHz, CMOS VCO
    A. Tsitouras, F. Plessas.
    Circuits, Systems and Signal Processing, vol. 30, no. 2, Apr. 2011, pp. 263-285.  
  14. A study of superharmonic injection locking in multiband frequency dividers
    F. Plessas.
    International Journal of Circuit Theory and Applications, vol. 39, Issue 4, April 2011, pp. 397-410. 
  15. Phase noise characterization of subharmonic injection locked oscillators
    F. Plessas, A. Tsitouras and G. Kalivas.
    International Journal of Circuit Theory and Applications, vol. 39, Issue 7, July 2011, pp. 791-800. 
  16. A linear, ultra wideband, low power, 2.1-5 GHz VCO
    A. Tsitouras, F. Plessas and G. Kalivas.
    International Journal of Circuit Theory and Application, vol. 39, Issue 8, Aug. 2011, pp. 823-833. 
  17. 5-GHz fully differential multifunctional circuit
    F. Plessas A. Tsitouras, and G. Kalivas.
    International Journal of Electronics, vol. 99, Issue 9, pp. 1317-1322.  
  18. Phase noise performance of fully differential sub-harmonic injection-locked PLL
    F. Plessas, F. Gioulekas, and G. Kalivas.
    IET Electronics Letters, vol. 46, Issue 19, Sep. 2010, pp.1319-1321.  
  19. A 1-GHz, DDR2/3 SSTL Driver with On-Die Termination, Strength Calibration, and Slew Rate Control
    F. Plessas, E. Davrazos, A. Alexandropoulos, M. Birbas.
    Computers and Electrical Engineering, vol. 38, no. 2, Mar. 2012.  
  20. Advanced Calibration Techniques for High Speed Source-Synchronous Interfaces
    F. Plessas, A. Alexandropoulos, S. Koutsomitsos, E. Davrazos, M. Birbas.
    IET Computers & Digital Techniques, vol. 5, Issue 5, Sep. 2011, pp. 366-374.  
  21. A sub-1V supply CMOS voltage reference generator
    A. Tsitouras, F. Plessas, M. Birbas, J. Kikidis, G. Kalivas.
    International Journal of Circuit Theory and Applications, vol. 40, Issue 8, Aug. 2012, pp. 745-758. 
  22. A 1 V CMOS Programmable Accurate Charge Pump with Wide Output Voltage Range
    A. Tsitouras, F. Plessas, M. Birbas, G. Kalivas.
    Microelectronics Journal, vol. 42, Issue 9, Sep. 2011, pp. 1082-1089.  
  23. A pseudo-FG technique for efficient energy harvesting
    G. Giannakas, F. Plessas, G. Stamoulis.
    IET Electronics Letters, vol. 48, no. 9, April 2012.  
  24. A 90nm CMOS 15/60 GHz frequency quadrupler
    G. Souliotis, F. Plessas, F. Liakou, M. Birbas.
    International Journal of Electronics, Dec 2012. 
  25. A 5Gbps USB3.0 Transmitter and Receiver Linear Equalizer
    N. Terzopoulos, C. Laoudias, F. Plessas, G. Souliotis, S. Koutsomitsos and M. Birbas.
    International Journal of Circuit Theory and Applications, 43(7), pp. 900 - 916, July 2015.  
  26. Phase interpolator with improved linearity
    G. Souliotis, C. Laoudias, F. Plessas and N. Terzopoulos.
    Circuits, Systems and Signal Processing, May 29, 2015  
  27. A high accuracy voltage reference generator
    G. Souliotis, F. Plessas, S. Vlassis.
    Microelectronics Journal, vol. 75, Issue 9, May 2018, pp. 61-67.  
  28. A 76–84 GHz CMOS 4× Subharmonic Mixer With Internal Phase Correction
    F. Plessas, G. Souliotis, and R. Makri.
    IEEE Transactions on Circuits and Systems I, vol. 65, no. 7, July 2018, pp. 2083 - 2096.  
  29. Conventional and Machine Learning Approaches as Countermeasures Against Hardware Trojan Attacks
    KG. Liakos, GK. Georgakilas, S. Moustakidis, N. Sklavos and FC. Plessas.
    ELSEVIER Microprocessors and Microsystems, vol. 79, November 2020.  
  30. GAINESIS: Generative Artificial Intelligence NEtlists SynthesIS
    KG. Liakos, GK. Georgakilas, FC. Plessas and P. Kitsos.
    MDPI Electronics, vol. 11, issue 2, 13 January 2022.  
Conference Papers
  1. Multiple Overlapping Register Files for Micronet Clusters
    D. K. Arvind and C. P. Sotiriou.
    Proceedings of the 2nd UK Asynchronous Forum, Newcastle 1998.  
  2. Wireless Data Transfer System
    F. Plessas, A. Miaoudakis, Gr. Kalivas, K. Efstathiou.
    Technology and industrial applications of power electronics - industrial electronics, Athens, Sep. 28-29, 2000.  
  3. Direct-Mapped Asynchronous Finite-State Machines in CMOS Technology
    C. Sotiriou.
    Proceedings of the IEEE ASIC/SOC 2001 Conference, Washington D.C., 5 pages, September 2001.  
  4. Read, Use, Simulate, Experiment and Build: An Integrated Approach for Teaching Computer Architecture
    I. Papaefstathiou and C. Sotiriou.
    Workshop on Computer Architecture Education (WCAE 2002), held in conjunction with the 29th International Sumposium on Computer Architecture, Anchorage, Alaska, USA, May 2002.  
  5. Implementing Asynchronous Circuits using a Conventional EDA Tool- Flow
    C. Sotiriou.
    Proceedings of the 39th ACM/IEEE Design Automation Conference (DAC), pp. 415-418, New Orleans, USA, July 2002. 
  6. A Concurrent Model for De-Synchronization
    J. Cortadella, A. Kondratyev, L. Lavagno and C. P. Sotiriou.
    Proceedings of the 12th (ACM/IEEE) International Workshop on Logic and Synthesis (IWLS), 10 pages, Laguna Beach, California, USA, May 2003. 
  7. Automating the Design of an Asynchronous DLX Microprocessor
    M. Amde, I. Blunno and C. P. Sotiriou.
    Proceedings of the 40th ACM/IEEE Design Automation Conference (DAC), pp. 502-507, Anaheim, California, USA, July 2003.
  8. Desynchronisation: Asynchronous Circuits from Syn- chronous Specifications
    C. Sotiriou and L. Lavagno.
    Proceedings of the IEEE International SOC 2003 Conference, 4 pages, Portland, Oregon, USA, September 2003.
  9. Locking Techniques For RF Oscillators at 5-6 GHz Frequency Range
    F. Plessas, G. Kalivas.
    Proc. 10th IEEE International Conference on Electronics, Circuits and Systems, United Arab Emirates, December 14 -17, 2003.
  10. Locking Techniques For RF Oscillators at 5-6 GHz Frequency Range
    F. Plessas, G. Kalivas.
    Proc. 10th IEEE International Conference on Electronics, Circuits and Systems, United Arab Emirates, December 14 -17, 2003.
  11. Design-Space Exploration of a Cryptography Algorithm
    C. Sotiriou and Y. Papaefstathiou.
    Proceedings of the 10th IEEE International Conference on Electronics, Circuits and Systems (ICECS), pp. 858-861, Vol. 2, United Arab Emirates, December 2003.
  12. A 5 GHz Low noise Amplifier On 0.35um BiCMOS SiGe
    F. Plessas, G. Kalivas.
    Proc. 10th IEEE International Conference on Electronics, Circuits and Systems, United Arab Emirates, December 14 -17, 2003.
  13. 3LSSD: Automatic Scan Insertion and Pattern Generation for Asynchronous Circuits
    A. Efthymiou and C. P. Sotiriou
    Proceedings of the Design Automation and Test in Europe Conference (DATE), pp. 672-673, Vol. 1, Paris, February 2004.
  14. Data Synchronisation Issues in GALS SoCs
    R. Dobkin, R. Ginosar and C. P. Sotiriou
    Proceedings of the 10th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC), pp. 170-180, Crete, Greece, 2004.
  15. Handshake Protocols for De-Synchronisation
    I. Blunno, J. Cortadella, A. Kondratyev, L. Lavagno, K. Lwin and C. P. Sotiriou
    Proceedings of the 10th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC), pp. 149-158, Crete, Greece, 2004.
    Received Best Paper Award
  16. A 5-GHz, Variable Gain, SiGe Low Noise Amplifier
    F. Plessas, G. Kalivas.
    Proc. 24th International Conference on Microelectronics, Nis, Serbia and Montenegro, May 16-19, 2004.
  17. Design and Implementation of a Dual-Loop Frequency Synthesizer for 5 GHz WLANs
    F. Plessas, S. Vatti, G. Kalivas.
    Proc. 24th International Conference on Signals and Electronic Systems, Poznan, Poland, September 13-15, 2004.
  18. Coping with the variability of combinational logic delays
    J. Cortadella, A. Kondratyev, L. Lavagno and C. P. Sotiriou.
    Proceedings of the 2004 IEEE International Con- ference on Computer Design (ICCD 2004), 4 pages, San Jose, October 2004.
  19. Controlling Event Spacing in Self-Timed Rings
    V. Zebilis, C. P. Sotiriou.
    Proceedings of the 11th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC), pp. 109 - 115, New York City, USA, March 2005.
  20. Actual Delay Circuits on FPGA : Trading-Off LUTS for Speed
    E. Kasapaki, P. Matthaiakis and C. P. Sotiriou.
    Proceedings of the 16th IEEE International Conference on Field Programmable Logic and Applications, 6 pages, Spain, August 2006.
  21. A Subharmonic Injection-Locked Self-Oscillating Mixer
    F. Plessas, A. Papalambrou and G. Kalivas.
    Proc. 2007 IEEE International Symposium on Circuits and Systems, New Orleans, May 27-30, 2007.
  22. A Fully-automated Desyn-chronization Flow for Synchronous Circuits
    N. Andrikos, L. Lavagno, D. Pandini and C. P. Sotiriou
    Proceedings of the 44th ACM/IEEE Design Automation Conference (DAC), 6 pages, San Diego, California, USA, June 2007.
  23. Electronic Circuit Subsystems for Broadband Wireless Applications
    F. Plessas.
    Proc. EDAA PhD forum 2008 in conjunction with the Design, Automation and Test in Europe Conference (DATE), Munich, Germany, March 10-14, 2008.
  24. A novel 1.8V, 1066Mbps, DDR2, DFI-compatible Memory Interface
    A. Alexandropoulos, E. Davrazos, F. Plessas, M. Birbas.
    Proc. 2010 IEEE Annual Symposium on VLSI, Kefalonia, Greece, July 5-7, 2010.
  25. A dynamic DFI-compatible strobe qualification system for Double Data Rate (DDR) Physical Interfaces
    A. Alexandropoulos, F. Plessas, M. Birbas.
    Proc. 17th IEEE International Conference on Electronics, Circuits, and Systems (ICECS 2010), Athens, December 12-15, 2010.
  26. A 2.45GHz power harvesting circuit in 90nm CMOS
    G. Giannakas, F. Plessas, G. Nassopoulos, G. Stamoulis.
    Proc. 17th IEEE International Conference on Electronics, Circuits, and Systems (ICECS 2010), Athens, Greece, December 12-15, 2010.
  27. SCPlace: A Statistical Slack-Assignment Based Constructive Placer
    E. Kounalakis and C. P. Sotiriou
    Proceedings of the International Symposium on Quality Electronic Design (ISQED), 6 pages, Santa Clara, Califoria, USA, March 2011.
  28. CPlace: A Constructive Placer for Synchronous and Asynchronous Circuits
    E. Kounalakis and C. P. Sotiriou
    Proceedings of the 17th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC), 6 pages, Ithaca, NY, USA, April 2011.
  29. Statistical Timing-Based Post-Placement Leakage Recovery
    E. Kounalakis and C. P. Sotiriou
    Proceedings of the IEEE Computer Society Annual Symposium on VLSI, (ISVLSI), 6 pages, Chennai, India, July 2011
  30. A 60-GHz Quadrature PLL in 90nm CMOS
    F. Plessas, V. Panagiotopoulos, V. Kalenteridis, G. Souliotis, F. Liakou, S. Koutsomitsos, S. Siskos, A. Birbas.
    18th IEEE International Conference on Electronics, Circuits, and Systems (ICECS 2011), Beirut, Lebanon, December 11-14, 2011.
  31. Building blocks for a 15 GHz PLL in deep-submicron technology
    V. Kalenteridis, F. Plessas, V. Panagiotopoulos, S. Siskos.
    Pan-Hellenic Conference on Electronics and Telecommunications (PACET) 2012, Thessaloniki, Greece, March 16-18, 2012.
  32. A variable gain wideband CMOS low-noise amplifier for 75 MHz-3 GHz wireless receivers
    C. Vassou, F. Plessas, N. Terzopoulos.
    20th IEEE International Conference on Electronics, Circuits, and Systems (ICECS 2013), Abu Dhabi, UAE, December 8-11, 2013.
  33. A Polynomial Time Flow for Imple- menting Free-Choice Petri-Nets
    P. M. Mattheakis, C. P. Sotiriou and P. Beerel.
    30th IEEE International Conference on Computer Design (ICCD), 6 pages, Quebec, Canada, September 2012.
  34. Polynomial Complexity Asynchronous Control Circuit Synthesis of Concurrent Specifications based on Burst-Mode FSM Decomposition
    P. M. Mattheakis and C. P. Sotiriou.
    Proceedings of the 26th IEEE International Conference on VLSI Design (VLSID), 6 pages, Pune, India, January 2013.
  35. A 16-GHz Differential LC-VCO in 16-nm CMOS
    I. Zographopoulos, F. Plessas.
    Pan-Hellenic Conference on Electronics and Telecommunications (PACET) 2015, Ioannina, Greece, May 8-9, 2015.
  36. Low Power Monolithic 3D IC Design of Asynchronous AES Core
    N. Penmetsa, C. P. Sotiriou and S. K. Lim.
    Proceedings of the 21st IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC), 7 pages, Mountain View, California, USA, May 2015.
  37. Asynchronous Sub-Threshold Ultra-Low Power Processor
    R. Diamant, R. Ginosar and C. P Sotiriou.
    Proceedings of the 25th International Workshop on Power and Timing Modelling, Optimization and Simulation (PATMOS), 8 pages, Bahia, Brazil, September 2015.
  38. Heterogeneous Spectrum Bands Aggregation Prototype with Cognitive Radio Capabilities
    E. Antonopoulos, F. Plessas, F. Foukalas, I. Zographopoulos.
    IEEE International Conference on Microwaves, Communications, Antennas and Electronic Systems (COMCAS 2015), Tel Aviv, Israel, November 2-4, 2015.
  39. A 16-nm FinFET 16-GHz Differential LC-VCO
    I. Zographopoulos, F. Plessas, E. Antonopoulos, F. Foukalas.
    IEEE International Conference on Microwaves, Communications, Antennas and Electronic Systems (COMCAS 2015), Tel Aviv, Israel, November 2-4, 2015.
  40. Abax: 2D/3D Legaliser Supporting Look-Ahead Legalisation and Blockage Strategies
    N. Sketopoulos, C. P. Sotiriou and S. Simoglou.
    Proceedings of the Design Automation and Test in Europe (DATE) Conference, 4 pages, Dresden, Germany, March 2018.
  41. Machine Learning for Hardware Trojan Detection: A Review
    KG. Liakos, GK. Georgakilas, S. Moustakidis, P. Karlsson and FC. Plessas.
    Panhellenic Conference on Electronics and Telecommunications (PACET) Conference 2019.
  42. Hardware Trojan Classification at Gate-level Netlists based on Area and Power Machine Learning Analysis
    KG. Liakos, GK. Georgakilas and FC. Plessas.
    IEEE Computer Society Annual Symposium on VLSI Conference 2021.
Patents
  1. Asynchronous, Multi-Rail, Asymmetric-Phase, Static Digital Logic and Method for Designing the Same
    C. P. Sotiriou.
    U.S. P.T.O. Priority Application US11/283,070.
  2. System and Method of Determining the Speed of Digital Application Spe- cific Integrated Circuits - Speed Gauge
    C. P. Sotiriou.
    U.S. P.T.O. Priority Application US11/315,309, Issued January 2008 - Patent #7,318,003.
  3. System and Method of Determining the Speed of Digital Application Spe- cific Integrated Circuits - Error Signal
    C. P. Sotiriou.
    U.S. P.T.O. Priority Application US11/330,350.
  4. Apparatus And Method For Optimizing Delay Elements In Asynchronous Digital Circuits
    C. P. Sotiriou and S. Lymperis.
    U.S. P.T.O. Priority Application US11/933,230.
  5. System And Method for Reducing EME Emissions in Digital Desynchronized Circuits
    C. P. Sotiriou and S. Lymperis.
    U.S. P.T.O. Priority Application US112/003,468.
Books
  1. 60 GHz Millimeter-Wave WLANs and WPANs: Introduction, System Design, and PHY Layer Challenges
    F. Plessas, N. Terzopoulos.
    System-Level Design Methodologies for Telecommunication, Springer, 2014, pp. 63-78.
Referred Workshop Papers
  1. RF Prototype for Dynamic Cognitive Carrier Aggregation of Heterogeneous Dispersed Bands
    E. Antonopoulos, F. Plessas, F. Foukalas.
    Twelfth International Symposium on Wireless Communication Systems (ISWCS'15), WSH4: Third Workshop on Cognitive Radio for Fifth Generation Networks and Spectrum (CRAFT 2015), August 25th - 28th, 2015, Brussels, Belgium.
Invited Talks, Events and Reports
  1. Digital Wireless Communication Techniques Seminar - Lecture 4: Wireless Channel Modeling: Small-Scale Fading and Multipath
    F. Plessas.
    IEEE TESYD Student Branch, Nafpaktos, Greece, May 11, 2012.
  2. Millimeter-Wave WLANs & WPANs: Introduction, system design, and PHY layer challenges
    F. Plessas.
    3rd IEEE Greece GOLD A.G. ATHENA Summer School, Pyrgos, Greece, July 1-6, 2012.
  3. Analog Interface Design
    F. Plessas.
    Wireless Sensor Node Circuit and System Design - Wise Design 2015 workshop, powered by "IEEE CASS Outreach Initiative 2015", Aristotle University, Greece, Dec. 7 & 8, 2015.
  4. Sub-Harmonic Mixer and Low Noise Amplifier for 70-90 GHz single chip solutions
    F. Plessas, E. Tsimpinos, R. Makri.
    Europractice IC Service, Activity Report 2015.