Hardware trojans impact our everyday life and may even cause life threatening situations. Unlike other errors and malfunctions, trojans are inserted deliberately. Apart from insider attacks, the economically driven outsourcing of production steps to third party contractors enlarges the attack surface dramatically. Today, there is no single tool that can provide a holistic approach for hardware trojan detection covering both pre-silicon verification and post-silicon testing. HERO takes a significant step forward by developing an artificial intelligence empowered approach that will be capable of identifying vulnerable regions in IC designs as well as perform post-silicon validation to cover trojans of different types and sizes under large parameter variations. The deployment of HERO technology is expected to bring a breakthrough in numerous IC-related sectors including cell phones, digital cameras, microelectromechanical systems, photonics and bioelectronic devices.

An R&D collaborative project undertaken by Electronic Devices, Circuits and Systems Laboratory (electrolab), for NanoZeta Technologies Ltd., with the aim to develop a novel power management unit. CAS lab is responsible for the design of the LDOs and the DC-DC buck converters.

Members of the group are participating in the FP7 research project SOLDER. The goal of SOLDER is to develop a new spectrum overlay technology, which will provide the efficient aggregation of non-continuous dispersed spectrum bands licensed to heterogeneous networks (HetNets) and heterogeneous Radio Access Technology (h-RATs).

Members of the group are participating in the NSRF 2007-2013, National Action: Cooperation, research project EMOSIC. EMOSIC - An E-band / mmwave CMOS RFIC/MMIC implementation for future private networks and mobile backhaul radio applications.

Our aim is to implement CA techniques to provide extended bandwidth by aggregating up to five component carriers (CCs), where each CC could carry 5-20 MHz of bandwidth. Thus, an aggregated total bandwidth up to 100 MHz can be provided on a single chip with an initial target of maximum 5 CCs.

The design and implementation of this RF front-end ASIC is part of a multiband, adaptive, radio-frequency (RF) transceiver architecture for carrier aggregation, providing (i) interband contiguous and non-contiguous intra-band CA with the capability to receive and transmit up to three carriers simultaneously, (ii) both time-division duplex (TDD) and frequency-division duplex (FDD) modes, while demonstrating (iii) CA between licensed and unlicensed bands, (iv) MIMO capabilities and finally, (v) employing energy detection for spectrum sensing.

TWIN-RELECT (Twinning for Excellence in Reliable Electronics) is a European-funded project that aims to strengthen the research capacity of the University of Thessaly in the field of reliable electronic design. The project focuses on developing cross-layer methodologies for the design and analysis of reliable electronic systems, addressing challenges from device level up to system level. This is achieved through strategic collaboration with leading institutions, including the University of Manchester (UOM), IHP – Leibniz Institute for High Performance Microelectronics, CNRS, and the University of Montpellier. Through knowledge transfer, training, and joint research activities, TWIN-RELECT enhances excellence and innovation in reliable electronics.

This project explores the integration of Agentic Artificial Intelligence into Electronic Design Automation (EDA) workflows, in collaboration with Qualcomm. The goal is to accelerate chip design processes by enabling intelligent, autonomous decision-making throughout the design flow. By leveraging AI-driven agents, the approach aims to reduce design complexity, minimize human intervention, improve accuracy, and significantly enhance performance and productivity in modern semiconductor design.

CMOS2.0 is a next-generation research initiative led by imec that aims to go beyond traditional CMOS scaling limits. The project focuses on developing innovative technologies for smaller, faster, more energy-efficient, and sustainable microchips. It brings together leading universities and industry partners to explore new materials, device architectures, and system-level approaches that will define the future of semiconductor technology. CMOS2.0 plays a key role in shaping the next era of high-performance and energy-efficient computing systems.

ODE4EC-DIG (Open Design Environment for European Chips – Digital SoC Design) is a Horizon Europe Chips Joint Undertaking project focused on developing open-source Electronic Design Automation (EDA) tools for digital System-on-Chip (SoC) design.

The project aims to improve productivity and interoperability in chip design while reducing dependence on proprietary tools, supporting a more open and competitive European semiconductor ecosystem.

ODE4EC-AMS (Open Design Environment for European Chips – Analog and Mixed Signal) is a Horizon Europe Chips Joint Undertaking project focused on developing open-source Electronic Design Automation (EDA) tools for analog and mixed-signal design.

The project aims to enable scalable AMS/RF design frameworks and strengthen European technological sovereignty by advancing the open-source EDA ecosystem for mature semiconductor technologies.

The Hellenic Chips Competence Centre (HCCC) is Greece’s national hub for innovation, skills development, and collaboration in semiconductors and microelectronics. In alignment with the EU Chips Act, HCCC supports startups, SMEs, researchers, and industry through infrastructure, training, and technology transfer services. It also facilitates access to design platforms and pilot lines, helping strengthen the Greek and European semiconductor ecosystem.