Hardware trojans impact our everyday life and may even cause life threatening situations. Unlike other errors and malfunctions, trojans are inserted deliberately. Apart from insider attacks, the economically driven outsourcing of production steps to third party contractors enlarges the attack surface dramatically. Today, there is no single tool that can provide a holistic approach for hardware trojan detection covering both pre-silicon verification and post-silicon testing. HERO takes a significant step forward by developing an artificial intelligence empowered approach that will be capable of identifying vulnerable regions in IC designs as well as perform post-silicon validation to cover trojans of different types and sizes under large parameter variations. The deployment of HERO technology is expected to bring a breakthrough in numerous IC-related sectors including cell phones, digital cameras, microelectromechanical systems, photonics and bioelectronic devices.

An R&D collaborative project undertaken by Electronic Devices, Circuits and Systems Laboratory (electrolab), for NanoZeta Technologies Ltd., with the aim to develop a novel power management unit. CAS lab is responsible for the design of the LDOs and the DC-DC buck converters.

Members of the group are participating in the FP7 research project SOLDER. The goal of SOLDER is to develop a new spectrum overlay technology, which will provide the efficient aggregation of non-continuous dispersed spectrum bands licensed to heterogeneous networks (HetNets) and heterogeneous Radio Access Technology (h-RATs).

Members of the group are participating in the NSRF 2007-2013, National Action: Cooperation, research project EMOSIC. EMOSIC - An E-band / mmwave CMOS RFIC/MMIC implementation for future private networks and mobile backhaul radio applications.

Our aim is to implement CA techniques to provide extended bandwidth by aggregating up to five component carriers (CCs), where each CC could carry 5-20 MHz of bandwidth. Thus, an aggregated total bandwidth up to 100 MHz can be provided on a single chip with an initial target of maximum 5 CCs. The design and implementation of this RF front-end ASIC is part of a multiband, adaptive, radio-frequency (RF) transceiver architecture for carrier aggregation, providing (i) interband contiguous and non-contiguous intra-band CA with the capability to receive and transmit up to three carriers simultaneously, (ii) both time-division duplex (TDD) and frequency-division duplex (FDD) modes, while demonstrating (iii) CA between licensed and unlicensed bands, (iv) MIMO capabilities and finally, (v) employing energy detection for spectrum sensing.