CASlab GAINESIS Tool

A significant problem in the field of hardware security consists of hardware trojan (HT) viruses. The insertion of HTs into a circuit can be applied for each phase of the circuit chain of production. HTs degrade the infected circuit, destroy it or leak encrypted data. Nowadays, efforts are being made to address HTs through machine learning (ML) techniques, mainly for the gate-level netlist (GLN) phase, but there are some restrictions. Specifically, the number and variety of normal and infected circuits that exist through the free public libraries, such as Trust-HUB, are based on the few samples of benchmarks that have been created from circuits large in size. Thus, it is difficult, based on these data, to develop robust ML-based models against HTs. We propose a new deep learning (DL) tool named Generative Artificial Intelligence Netlists SynthesIS (GAINESIS) for the synthesis of new Trojan-Free and Trojan-Infected circuit samples at GLN phase. GAINESIS can solve the problem with the lack of samples but cannot remedy the problem of the lack of diversity in terms of size and function that is present in Trust-HUB and other freely accessible repositories.

Please cite the following papers when using GAINESIS tool for the synthesis of new datasets:

1) KG Liakos, GK Georgakilas, FC Plessas, Paris Kitsos "GAINESIS: Generative Artificial Intelligence NEtlists SynthesIS", Electronics, 2022

2) KG Liakos, GK Georgakilas, S Moustakidis, N Sklavos, FC Plessas "Conventional and Machine Learning Approaches as Countermeasures Against Hardware Trojan Attacks", Microprocessors and Microsystems, 2020

Hardware Trojan Problem

Every year, the rate at which technology is applied on areas of our everyday life is increasing at a steady pace. This rapid development drives the technology companies to design and fabricate their integrated circuits (ICs) in non-trustworthy outsourcing foundries to reduce the cost, thus, leaving space for a synchronous form of virus, known as Hardware Trojan (HT), to be developed. HTs leak encrypted information, degrade device performance or lead to total destruction. To reduce the risks associated with these viruses, various approaches have been developed aiming to prevent and detect them, based on conventional or machine learning methods. Ideally, any undesired modification made to an IC should be detectable by pre-silicon verification/simulation and post-silicon testing. The infected circuit can be inserted in different stages of the manufacturing process, rendering the detection of HTs a complicated procedure.

Countermeasures Against Hardware Trojan

Countermeasures against HTs are classified according four categories: 1) Conventional Hardware Trojan Detection Approaches (CHTDA), which have have as main aim the detection of an HT in a circuit. These methods can be divided in two sub-categories. Side-Channel Analysis (SCA), in which circuit parameters such as, temperature, delay and power are used and in Logic Testing (LT), where test patterns for HT detection are generated 2) Machine Learning for Hardware Trojan Countermeasures Approaches (MLfHTCA), which consists of five sub-categories: Reverse Engineering Improvement (REI), Real-Time Detection (RTD), Golden Model-Free (GMF), Gate-Level Netlists Detection (GLND) and Classification Approaches (CA). REI methods aim to improve the RE imaging phase, the executional time and minimize the faults which are produced when the RE methodology is applied as HT countermeasure. RTD approaches try to detect in real-time the HT attacks and disable the infected circuit or bypass it to ensure the normal operation of the IC. GMF approaches develop models for the classification of HTs and ICs without the need of golden models. In the GLND subcategory, gate-level netlist features are used. In CA, infected and uninfected circuits are classified based on various features such as, dominant attributes of HTs and/or side-channel measurements, 3) Design for Security (DfS) which consists of two sub-categories, the Approaches for Hardware Trojan Prevention (AfHTP) and the Approaches for Hardware Trojan Detection Facilitation (AfHTDF). Both aim to increase the difficulty for HT insertion into the IC mainly at design phase or facilitate the detection approaches. DfS consists of two sub-categories, the Approaches for Hardware Trojan Prevention (AfHTP) and the Approaches for Hardware Trojan Detection Facilitation (AfHTDF). Both aim to increase the difficulty for HT insertion into the IC mainly at design phase or facilitate the detection approaches, 4) Runtime Monitor (RM) that focus on identifying potentially undetectable attacks and the effects from an activated HT in a circuit. There are three sub-categories; Configurable Security Monitors (CSM), Variant-Based Parallel Execution (VBPE) and Hardware- Software Approaches (HSA).

Benchmark Distribution

Our benchmark distribution consists of a total 18 types of circuits. Specifically, our benchmark consists of 14 synchronous and 4 asynchronous circuits. Sychronous circuits are, AES, B15, ETHERNETMAC10GE, MEMCTRL, PIC16F84, RS232, S1423, S13207, S15850, S35932, S38417, S38584, VGALCD and WB_CONMAX. Asychronous circuits are, C2670, C3540, C5315 and C6288.

Machine Learning Benchmark Dataset Table Example